One for All, and All for One – A Flexible Approach to CMOS Line Scan Design

Our internal projects typically have names that are more “fun” than the part numbers that end up in our datasheets. I’ve been involved in projects with names ranging from star constellations and wine varieties to superheroes! A while back, I started working on a project called Cardinal. I didn’t think much of the name… until I saw the die label on the CMOS line scan sensor I was working on:  Porthos. I then came across Athos and deduced that Darta was none other than d’Artagnan. What could have inspired that?RGhannoum-StitchBlock

The idea behind Cardinal (not Dumas’s Richelieu) was to create a family of high-speed CMOS line scan image sensors that use one flexible architecture to create all variations. An improvement to one sensor flavor could be ported to all the others. Data from all the sensor flavors could be used to help qualify one sensor.

The motivation behind that is that different applications have different requirements, and we do like to try to give all our customers products that work for them. This is not always easy because designing a new CMOS sensor is a lengthy and costly process in an era where cost and time are becoming nearly as important as quality. Our team came up with a flexible architecture that allowed us to design different flavors (or musketeers if you prefer :)) with quick turnaround times, and reduced risk.

This scalable architecture allowed us to vary the resolution, pixel pitch and number of lines, with both monochrome and color variants. To be able to achieve that, a stitchable block was designed with a column readout circuit that can multiplex up to two rows in parallel in the analog domain feeding the signals to a standalone Correlated-Double-Sampling circuit followed by a standalone Analog-to-Digital-Converter. Each stitch slice routes the data through four readout chains per side. This hybrid column/standalone architecture allows us to scale the line rate and the number of rows with pixel pitch without being limited by the conversion time of the digitizer.

By combining a varying number of stitch blocks, we are able to achieve resolutions ranging between 1k- and 8k-pixels per row.

RGhannoum-StitchableResolutionThe pixel pitch can be scaled from 7um to 10.5um and 14um, by spanning 1, 1.5 or 2 column circuit blocks.


For pixel pitches spanning more than one column circuit block, we can add additional rows. This approach allows us to create single-line to quad-line devices.

This also made it possible to have multi-line monochrome variants with zero line-spacing, multi-line color variants with spatially separated Red, Blue and Green rows to minimize crosstalk, and to double-up the Blue rows or add a Monochrome row for the quad-line device.


I think our musketeers lived up to their motto of standing united, but what do you think? Are there any other options/variants you can think of?

If you would like to get some more insight into our architecture, you could also join the Teledyne DALSA team at the upcoming International Image Sensor Workshop (June 12-16, 2013 in Snowbird, Utah, U.S.A).


About Roula

Roula is part of the Teledyne DALSA CMOS Product Development team. She holds a Bachelor's degree in Computer Engineering and a Master's of Applied Sciences degree in Electrical Engineering. Her hobbies include painting, reading, table-tennis and swimming.
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