A Second Life for Camera Link

In my previous post, “Will USB3 Vision overtake Camera Link?”, I questioned the ability of Camera Link to face the challenge raised by USB3 Vision. Since its introduction in 2000, Camera CameraLinkLink has reigned as the “go to” standard for real-time data acquisition from a machine vision camera. And for many years, commercial interfaces such as Firewire, GigE and now USB3 have been raising the bar on  acquisition throughput without a frame grabber. For many of us, this brings the equation of cost vs. bandwidth to the forefront of the interface debate.

Camera Link 2.0, released in February of 2012 is significant because it integrates many hanging appendices about cabling, power-over-cable, Windows 64-bit support, and 10-tap acquisition. Of particular interest is the standardization of “10-tap @ 8-bit” which when coupled with a maximum clock speed of 85 MHz, provides a sustainable 850 MB/s throughput. Not bad for a 10-year-old technology!

Since it’s creation, the Camera Link specification has depended on a specific family of chipsets, called Channel Link, (by National Semiconductor). But this is changing. FPGAs have evolved to enable them to directly drive Camera Link cables through their SERDES (serializer/deserializer). This innovative technique was proposed by JIIA members as early as 2007 at the Vision Show in Stuttgart (at least, this is my recollection). Nowadays, we are seeing many Camera Link products that do not use the Channel Link chip, even though it is a requirement in the spec. Does this mean that all camera and frame grabber vendors are cheaters? Not really, what it means is that FPGA interconnects are now so efficient they can replace the National Semiconductor part at a much lower price.

And what does this have to do with the arrival of USB3 Vision? Well, thanks to Xilinx, Altera and other FPGA manufacturers, these FPGAs are becoming more and more efficient and they can be combined with pre-emphasis and equalizers to further improve signal integrity, which means 2 things:

  1. The maximum cable length for an 85 MHz pixel clock can be greatly improved from the typical 7 meters that can be achieved using Channel Link parts.
  2. Or alternatively, for a given 7-meter cable, the pixel clock can be increased well beyond 85 MHz (equivalent to 850 MB/s transfer) while maintaining the bit error rate.

It is the latter of the two that could prove truly interesting as it increases the available bandwidth supported by a Camera Link system to surpass USB3 Vision.

’til next time,

 

About Eric

Eric is in charge of R&D activities at the Montreal office of Teledyne DALSA where he is surrounded by talented people working on the technologies of tomorrow. Chair of the GigE Vision committee, he enjoys reading and writing machine vision standards, especially the thicker ones.
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